#include "sys.h"
#include <stdio.h>

/**********************通用宏定义****************************/
#define BQ79616_NUM			4	//4个BQ79616菊花连接
#define CELLNUM_P_DEV		16	//每个芯片检测的电芯电压数量
#define CELLNUM_P_TEM		2	//每个芯片检测的电芯温度数量

/**@name    地址的宏定义值
* @{
*/
#define BQ79600_ADR 	0
#define BQ79616_ADR_S1	1
#define BQ79616_ADR_S2	2
#define BQ79616_ADR_S3	3
#define BQ79616_ADR_S4	4
/**@} */

#define VLSB_ADC 			0.19073f//电芯采集的LSB精度	 mV
#define VLSB_TSREF			0.16954f//TSREF采集的LSB精度 mV
#define VLSB_GPIO			0.15259f//GPIO采集的LSB精度，mV
#define VLSB_MAIN_DIETEMP1	0.025f	//die温度采集的LSB精度 ℃
#define VLSB_AUX_DIETEMP1	0.025f	//die温度采集的LSB精度 ℃

#define VLSB_AUX_BAT	0.0305f		//BAT电压采集的LSB精度 0.1V 
#define VLSB_BB			0.03052f	//BASBAR的电压采集的LSB精度 mV

extern u8 Bq79600_BUFFER[4096];

/************************寄存器宏定义************************/

/**@name    寄存器地址值
* @{
*/
#define S_DIR0_ADDR_OTP			0x00
#define S_DIR1_ADDR_OTP			0x01
#define S_DEV_CONF				0x02
#define S_ACTIVE_CELL			0x03
#define S_OTP_SPARE12			0x04
#define S_BB_POSN1				0x05
#define S_BB_POSN2				0x06
#define S_ADC_CONF1				0x07
#define S_ADC_CONF2				0x08
#define S_OV_THRESH				0x09
#define S_UV_THRESH				0x0A
#define S_OTUT_THRESH			0x0B
#define S_GPIO_CONF1			0x0C
#define S_GPIO_CONF2			0x0D
#define S_GPIO_CONF3			0x0E
#define S_GPIO_CONF4			0x0F
#define S_FAULT_MSK1			0x10
#define S_FAULT_MSK2			0x11
#define S_PWR_TRANSIT_CONF		0x12
#define S_COMM_TIMEOUT_CONF		0x13
#define S_TX_HOLD_OFF			0x14
#define S_MAIN_ADC_GAIN			0x15
#define S_MAIN_ADC_OFFSET		0x16
#define S_AUX_ADC_GAIN			0x17
#define S_AUX_ADC_OFFSET		0x18

#define S_CUST_MISC1			0x1B
#define S_CUST_MISC2			0x1C
#define S_CUST_MISC3			0x1D
#define S_CUST_MISC4			0x1E
#define S_CUST_MISC5			0x1F
#define S_CUST_MISC6			0x20
#define S_CUST_MISC7			0x21
#define S_CUST_MISC8			0x22

#define S_OTP_SPARE11			0x23
#define S_OTP_SPARE10			0x24
#define S_OTP_SPARE9			0x25
#define S_OTP_SPARE8			0x26
#define S_OTP_SPARE7			0x27
#define S_OTP_SPARE6			0x28
#define S_OTP_SPARE5			0x29
#define S_OTP_SPARE4			0x2A
#define S_OTP_SPARE3			0x2B
#define S_OTP_SPARE2			0x2C
#define S_OTP_SPARE1			0x2D
#define S_CUST_CRC_HI			0x2E
#define S_CUST_CRC_LO			0x2F

#define S_OTP_PROG_UNLOCK1A		0x300
#define S_OTP_PROG_UNLOCK1B		0x301
#define S_OTP_PROG_UNLOCK1C		0x302
#define S_OTP_PROG_UNLOCK1D		0x303

#define S_DIR0_ADDR				0x306
#define S_DIR1_ADDR				0x307
#define S_COMM_CTRL				0x308
#define S_CONTROL1				0x309
#define S_CONTROL2				0x30A
#define S_OTP_PROG_CTRL			0x30B

#define S_ADC_CTRL1				0x30D
#define S_ADC_CTRL2				0x30E
#define S_ADC_CTRL3				0x30F

#define S_CB_CELL16_CTRL		0x318
#define S_CB_CELL15_CTRL		0x319
#define S_CB_CELL14_CTRL		0x31A
#define S_CB_CELL13_CTRL		0x31B
#define S_CB_CELL12_CTRL		0x31C
#define S_CB_CELL11_CTRL		0x31D
#define S_CB_CELL10_CTRL		0x31E
#define S_CB_CELL9_CTRL			0x31F
#define S_CB_CELL8_CTRL			0x320
#define S_CB_CELL7_CTRL			0x321
#define S_CB_CELL6_CTRL			0x322
#define S_CB_CELL5_CTRL			0x323
#define S_CB_CELL4_CTRL			0x324
#define S_CB_CELL3_CTRL			0x324
#define S_CB_CELL2_CTRL			0x326
#define S_CB_CELL1_CTRL			0x327

#define S_VMB_DONE_THRESH		0x328
#define S_MB_TIMER_CTRL			0x329
#define S_VCB_DONE_THRESH		0x32A
#define S_OTCB_THRESH			0x32B
#define S_OVUV_CTRL				0x32C
#define S_OTUT_CTRL				0x32D
#define S_BAL_CTRL1				0x32E
#define S_BAL_CTRL2				0x32F

#define S_FAULT_RST1			0x331
#define S_FAULT_RST2			0x332
#define S_DIAG_OTP_CTRL			0x335
#define S_DIAG_COMM_CTRL		0x336
#define S_DIAG_PWR_CTRL			0x337
#define S_DIAG_CBFET_CTRL1		0x338
#define S_DIAG_CBFET_CTRL2		0x339
#define S_DIAG_COMP_CTRL1		0x33A
#define S_DIAG_COMP_CTRL2		0x33B
#define S_DIAG_COMP_CTRL3		0x33C
#define S_DIAG_COMP_CTRL4		0x33D
#define S_DIAG_PROT_CTRL		0x33E

#define S_OTP_ECC_DATAIN1		0x343
#define S_OTP_ECC_DATAIN2		0x344
#define S_OTP_ECC_DATAIN3		0x345
#define S_OTP_ECC_DATAIN4		0x346
#define S_OTP_ECC_DATAIN5		0x347
#define S_OTP_ECC_DATAIN6		0x348
#define S_OTP_ECC_DATAIN7		0x349
#define S_OTP_ECC_DATAIN8		0x34A
#define S_OTP_ECC_DATAIN9		0x34B
#define S_OTP_ECC_TEST			0x34C
#define S_SPI_CONF				0x34D
#define S_SPI_TX3				0x34E
#define S_SPI_TX2				0x34F
#define S_SPI_TX1				0x350
#define S_OTP_PROG_UNLOCK2A		0x351
#define S_OTP_PROG_UNLOCK2B		0x352
#define S_OTP_PROG_UNLOCK2C		0x353
#define S_OTP_PROG_UNLOCK2D		0x354

#define S_DEBUG_CTRL_UNLOCK		0x700
#define S_DEBUG_COMM_CTRL1		0x701
#define S_DEBUG_COMM_CTRL2		0x702

#define S_PARTID				0x500
#define S_DIE_ID1				0x501
#define S_DIE_ID2				0x502
#define S_DIE_ID3				0x503
#define S_DIE_ID4				0x504
#define S_DIE_ID5				0x505
#define S_DIE_ID6				0x506
#define S_DIE_ID7				0x507
#define S_DIE_ID8				0x508
#define S_DIE_ID9				0x509

#define S_CUST_CRC_RSLT_HI		0x50C
#define S_CUST_CRC_RSLT_LO		0x50D
#define S_OTP_ECC_DATAOUT1		0x510
#define S_OTP_ECC_DATAOUT2		0x511
#define S_OTP_ECC_DATAOUT3		0x512
#define S_OTP_ECC_DATAOUT4		0x513
#define S_OTP_ECC_DATAOUT5		0x514
#define S_OTP_ECC_DATAOUT6		0x515
#define S_OTP_ECC_DATAOUT7		0x516
#define S_OTP_ECC_DATAOUT8		0x517
#define S_OTP_ECC_DATAOUT9		0x518

#define S_OTP_PROG_STAT			0x519
#define S_OTP_CUST1_STAT		0x51A
#define S_OTP_CUST2_STAT		0x51B

#define S_SPI_RX3				0x520
#define S_SPI_RX2				0x521
#define S_SPI_RX1				0x522
#define S_DIAG_STAT				0x527
#define S_ADC_STAT1				0x528
#define S_ADC_STAT2				0x529
#define S_GPIO_STAT				0x52A
#define S_BAL_STAT				0x52B
#define S_DEV_STAT				0x52C
#define S_FAULT_SUMMARY			0x52D

#define S_FAULT_COMM1			0x530
#define S_FAULT_COMM2			0x531
#define S_FAULT_COMM3			0x532

#define S_FAULT_OTP				0x535
#define S_FAULT_SYS				0x536
#define S_FAULT_PROT1			0x53A
#define S_FAULT_PROT2			0x53B
#define S_FAULT_OV1				0x53C
#define S_FAULT_OV2				0x53D
#define S_FAULT_UV1				0x53E
#define S_FAULT_UV2				0x53F

#define S_FAULT_OT				0x540
#define S_FAULT_UT				0x541
#define S_FAULT_COMP_GPIO		0x543
#define S_FAULT_COMP_VCCB1		0x545
#define S_FAULT_COMP_VCCB2		0x546
#define S_FAULT_COMP_VCOW1		0x548
#define S_FAULT_COMP_VCOW2		0x549
#define S_FAULT_COMP_CBOW1		0x54B
#define S_FAULT_COMP_CBOW2		0x54C
#define S_FAULT_COMP_CBFET1		0x54E
#define S_FAULT_COMP_CBFET2		0x54F

#define S_FAULT_COMP_MISC		0x550
#define S_FAULT_PWR1			0x552
#define S_FAULT_PWR2			0x553
#define S_FAULT_PWR3			0x554
#define S_CB_COMPLETE1			0x556
#define S_CB_COMPLETE2			0x557


#define S_VCELL16_HI			0x568
#define S_VCELL16_LO			0x569
#define S_VCELL15_HI			0x56A
#define S_VCELL15_LO			0x56B
#define S_VCELL14_HI			0x56C
#define S_VCELL14_LO			0x56D
#define S_VCELL13_HI			0x56E
#define S_VCELL13_LO			0x56F
#define S_VCELL12_HI			0x570
#define S_VCELL12_LO			0x571
#define S_VCELL11_HI			0x572
#define S_VCELL11_LO			0x573
#define S_VCELL10_HI			0x574
#define S_VCELL10_LO			0x575
#define S_VCELL9_HI				0x576
#define S_VCELL9_LO				0x577
#define S_VCELL8_HI				0x578
#define S_VCELL8_LO				0x579
#define S_VCELL7_HI				0x57A
#define S_VCELL7_LO				0x57B
#define S_VCELL6_HI				0x57C
#define S_VCELL6_LO				0x57D
#define S_VCELL5_HI				0x57E
#define S_VCELL5_LO				0x57F
#define S_VCELL4_HI				0x580
#define S_VCELL4_LO				0x581
#define S_VCELL3_HI				0x582
#define S_VCELL3_LO				0x583
#define S_VCELL2_HI				0x584
#define S_VCELL2_LO				0x585
#define S_VCELL1_HI				0x586
#define S_VCELL1_LO				0x587


#define S_BUSBAR_HI				0x588
#define S_BUSBAR_LO				0x589
#define S_TSREF_HI				0x58C
#define S_TSREF_LO				0x58D

#define S_GPIO1_HI				0x58E
#define S_GPIO1_LO				0x58F
#define S_GPIO2_HI				0x590
#define S_GPIO2_LO				0x591
#define S_GPIO3_HI				0x592
#define S_GPIO3_LO				0x593
#define S_GPIO4_HI				0x594
#define S_GPIO4_LO				0x595
#define S_GPIO5_HI				0x596
#define S_GPIO5_LO				0x597
#define S_GPIO6_HI				0x598
#define S_GPIO6_LO				0x599
#define S_GPIO7_HI				0x59A
#define S_GPIO7_LO				0x59B
#define S_GPIO8_HI				0x59C
#define S_GPIO8_LO				0x59D

#define S_DIETEMP1_HI			0x5AE
#define S_DIETEMP1_LO			0x5AF
#define S_DIETEMP2_HI			0x5B0
#define S_DIETEMP2_LO			0x5B1
#define S_AUX_CELL_HI			0x5B2
#define S_AUX_CELL_LO			0x5B3
#define S_AUX_GPIO_HI			0x5B4
#define S_AUX_GPIO_LO			0x5B5
#define S_AUX_BAT_HI			0x5B6
#define S_AUX_BAT_LO			0x5B7
#define S_AUX_REFL_HI			0x5B8
#define S_AUX_REFL_LO			0x5B9
#define S_AUX_VBG2_HI			0x5BA
#define S_AUX_VBG2_LO			0x5BB
#define S_AUX_VBG5_HI			0x5BC
#define S_AUX_VBG5_LO			0x5BD
#define S_AUX_AVAO_REF_HI		0x5BE
#define S_AUX_AVAO_REF_LO		0x5BF
#define S_AUX_AVDD_REF_HI		0x5C0
#define S_AUX_AVDD_REF_LO		0x5C1
#define S_AUX_OV_DACHI			0x5C2
#define S_AUX_OV_DAC_LO			0x5C3
#define S_AUX_UV_DAC_HI			0x5C4
#define S_AUX_UV_DAC_LO			0x5C5
#define S_AUX_OT_OTCB_DAC_HI	0x5C6
#define S_AUX_OT_OTCB_DAC_LO	0x5C7
#define S_AUX_UT_DAC_HI			0x5C8
#define S_AUX_UT_DAC_LO			0x5C9
#define S_AUX_VCBDONE_DAC_HI	0x5CA
#define S_AUX_VCBDONE_DAC_LO	0x5CB
#define S_AUX_VCM1_HI			0x5CC
#define S_AUX_VCM1_LO			0x5CD
#define S_VCM2_HI				0x5CE
#define S_VCM2_LO				0x5CF

#define S_DEBUG_COMM_STAT		0x780
#define S_DEBUG_UART_RC			0x781
#define S_DEBUG_UARTR_RR		0x782
#define S_DEBUG_COMH_BIT		0x783
#define S_DEBUG_COMH_RC			0x784
#define S_DEBUG_COMH_RR_TR		0x785
#define S_DEBUG_COML_BIT		0x786
#define S_DEBUG_COML_RC			0x787
#define S_DEBUG_COML_RR_TR		0x788
#define S_DEBUG_UART_DISCARD	0x789
#define S_DEBUG_COMH_DISCARD	0x78A
#define S_DEBUG_COML_DISCARD	0x78B
#define S_DEBUG_UART_VALID_HI	0x78C
#define S_DEBUG_UART_VALID_LO	0x78D
#define S_DEBUG_COMH_VALID_HI	0x78E
#define S_DEBUG_COMH_VALID_LO	0x78F
#define S_DEBUG_COML_VALID_HI	0x790
#define S_DEBUG_COML_VALID_LO	0x791
#define S_DEBUG_OTP_SEC_BLK		0x7A0
#define S_DEBUG_OTP_DED_BLK		0x7A1
/**@} */

/**@brief   ADC的GAIN和OFFSET 读取及设置计算
* @{
*/
/***************获取*******************/
#ifndef GET_MAIN_ADC_GAIN	
	#define GET_MAIN_ADC_GAIN(x) 	x * 0.0031f - 0.390625f	//根据数据手册
#endif

#ifndef GET_MAIN_ADC_OFFSET	
	#define GET_MAIN_ADC_OFFSET(x) 	x * 0.19073f - 24.41406f
#endif

#ifndef GET_AUX_ADC_GAIN	
	#define GET_AUX_ADC_GAIN(x) 	x * 0.390625f - 0.0031f
#endif

#ifndef GET_AUX_ADC_OFFSET	
	#define GET_AUX_ADC_OFFSET(x) 	x * 0.19073f - 24.41406f
#endif

/***************设置*******************/
#ifndef SET_MAIN_ADC_GAIN	
	#define SET_MAIN_ADC_GAIN(x) 	(u8)((x + 0.390625f) * 322.5806f)	//根据数据手册，同时把÷改为×
#endif

#ifndef SET_MAIN_ADC_OFFSET	
	#define SET_MAIN_ADC_OFFSET(x) 	(u8)((x + 24.41406f) * 5.2430f)
#endif

#ifndef SET_AUX_ADC_GAIN	
	#define SET_AUX_ADC_GAIN(x) 	(u8)((x + 0.390625f) * 322.5806f)	
#endif

#ifndef SET_AUX_ADC_OFFSET	
	#define SET_AUX_ADC_OFFSET(x) 	(u8)((x + 24.41406f) * 5.2430f)
#endif
/**@} */

/**@name    寄存器宏定义的值
* @{
*/
#define S_FAULT_IN_EN		0x01	//GPIO8作为NFAULT
#define S_FAULT_IN_DIS		0x00	//禁止GPIO8作为NNFAULT
#define S_SPI_MASTER_EN		0x01	//GPIO作为SPI使能
#define S_SPI_MASTER_DIS	0x00	//GPIO作为SPI禁止
#define S_GPIO_HIGHZ		0x00	//高阻态
#define S_GPIO_ADC_OTUT		0x01	//ADC and OTUT input 
#define S_GPIO_ADC_ONLY		0x02	//ADC only
#define S_GPIO_DIGI_INPUT	0x03	//数字输入
#define S_GPIO_OUT_HIGH		0x04	//输出高电平
#define S_GPIO_OUT_LOW		0x05	//输出低电平

#define CELL_10S			0x04	//10串电芯
#define CELL_11S			0x05	//11串电芯
#define CELL_12S			0x06	//12串电芯
#define CELL_13S			0x07	//13串电芯
#define CELL_14S			0x08	//14串电芯
#define CELL_15S			0x09	//15串电芯
#define CELL_16S			0x0A	//16串电芯

#define MAIN_ADC_DIS			0x00	//禁止main ADC运行
#define MAIN_ADC_SING_RUN		0x01	//单次运行
#define MAIN_ADC_CONTINOU		0x02	//连续运行

#define TWARN_85C 			0x00	//device T warining thresh 
#define TWARN_90C 			0x01
#define TWARN_105C 			0x02
#define TWARN_115C 			0x03

#define SLP_TIME_NO 		0x00
#define SLP_TIME_5S 		0x01
#define SLP_TIME_10S 		0x02
#define SLP_TIME_1MIN 		0x03
#define SLP_TIME_10MIN 		0x04
#define SLP_TIME_30MIN 		0x05
#define SLP_TIME_1HOUR 		0x06
#define SLP_TIME_2HOUR 		0x07

#define CTS_TIME_DIS 		0x00
#define CTS_TIME_100MS 		0x01
#define CTS_TIME_2S 		0x02
#define CTS_TIME_10S 		0x03
#define CTS_TIME_1MIN 		0x04
#define CTS_TIME_10MIN 		0x05
#define CTS_TIME_30MIN 		0x06
#define CTS_TIME_1HOUR 		0x07

#define CTL_SLP 			0x00	//sleep
#define CTL_SHD 			0x01	//shot dowm

#define CTL_TIME_DIS 		0x00
#define CTL_TIME_100MS 		0x01
#define CTL_TIME_2S 		0x02
#define CTL_TIME_10S 		0x03
#define CTL_TIME_1MIN 		0x04
#define CTL_TIME_10MIN 		0x05
#define CTL_TIME_30MIN 		0x06
#define CTL_TIME_1HOUR 		0x07

#define LPF_VCELL_6P5 		0x0	//6.5Hz (154 ms average
#define LPF_VCELL_13  		0x1	//13Hz 77 ms average
#define LPF_VCELL_26  		0x2	//38 ms average
#define LPF_VCELL_53  		0x3	//19 ms average
#define LPF_VCELL_111 		0x4	//9 ms average
#define LPF_VCELL_240 		0x5	//4 ms average
#define LPF_VCELL_600 		0x6	//1.6 ms average

#define AUX_SETTLE_4P3 		0x0	//4.3ms
#define AUX_SETTLE_2P3 		0x1	//2.3ms
#define AUX_SETTLE_1P3 		0x2	//1.3ms
#define AUX_SETTLE_0P3 		0x3	//0.3ms

#define MIAN_ADC_DIS 		00B	
#define MIAN_ADC_SR 		01B	//Single run
#define MIAN_ADC_CR 		10B	//Continuous run

#define AUX_CELL_ALL 		0X00
#define AUX_CELL_Busbar 	0X01
#define AUX_CELL_CELL1	 	0X02
#define AUX_CELL_CELL2	 	0X03
#define AUX_CELL_CELL3	 	0X04
#define AUX_CELL_CELL4	 	0X05
#define AUX_CELL_CELL5	 	0X06
#define AUX_CELL_CELL6	 	0X07
#define AUX_CELL_CELL7	 	0X08
#define AUX_CELL_CELL8	 	0X09
#define AUX_CELL_CELL9	 	0X0A
#define AUX_CELL_CELL10	 	0X0B
#define AUX_CELL_CELL11	 	0X0C
#define AUX_CELL_CELL12	 	0X0D
#define AUX_CELL_CELL13	 	0X0E
#define AUX_CELL_CELL14	 	0X0F
#define AUX_CELL_CELL15	 	0X10
#define AUX_CELL_CELL16	 	0X11

#define AUX_MODE_DIS 		0x0	
#define AUX_MODE_SR 		0x1	//Single run
#define AUX_MODE_CR 		0x2	//Continuous run  AUX_GPIO

#define AUX_GPIO_ALL 		0x00
#define AUX_GPIO_1 			0x01
#define AUX_GPIO_2 			0x02
#define AUX_GPIO_3 			0x03
#define AUX_GPIO_4 			0x04
#define AUX_GPIO_5 			0x06
#define AUX_GPIO_6 			0x06
#define AUX_GPIO_7 			0x07
#define AUX_GPIO_8 			0x08

#define BALANCE_TIME_DIS  	 0x00	//stop 
#define BALANCE_TIME_10S  	 0x01	//10s
#define BALANCE_TIME_30S  	 0x02	//30s
#define BALANCE_TIME_60S  	 0x03	//60s
#define BALANCE_TIME_300S  	 0x04	//300s
#define BALANCE_TIME_10MIN   0x05	//10min
#define BALANCE_TIME_20MIN   0x06	
#define BALANCE_TIME_30MIN   0x07	
#define BALANCE_TIME_40MIN   0x08
#define BALANCE_TIME_50MIN   0x09
#define BALANCE_TIME_60MIN   0x0A
#define BALANCE_TIME_70MIN   0x0B
#define BALANCE_TIME_80MIN   0x0C
#define BALANCE_TIME_90MIN   0x0D
#define BALANCE_TIME_100MIN  0x0E
#define BALANCE_TIME_110MIN  0x0F
#define BALANCE_TIME_120MIN  0x10
#define BALANCE_TIME_150MIN  0x11	
#define BALANCE_TIME_180MIN  0x12	
#define BALANCE_TIME_210MIN  0x13	
#define BALANCE_TIME_240MIN  0x14	
#define BALANCE_TIME_270MIN  0x15	
#define BALANCE_TIME_300MIN  0x16	
#define BALANCE_TIME_330MIN  0x17	
#define BALANCE_TIME_360MIN  0x18	
#define BALANCE_TIME_390MIN  0x19	
#define BALANCE_TIME_420MIN  0x1A	
#define BALANCE_TIME_450MIN  0x1B	
#define BALANCE_TIME_480MIN  0x1C	
#define BALANCE_TIME_510MIN  0x1D	
#define BALANCE_TIME_540MIN  0x1E	
#define BALANCE_TIME_600MIN  0x1F	

#define VCB_THR_DIS 0x00 //Disables voltage based on CB_DONE comparison
#define VCB_THR_2P8 0x01 //stop
#define VCB_THR(x) ((x)>=(2800) ? ((x-2800)/25+1) : (0))//Range from 2.8 V to 4.35 V with 25-mV steps

#define OV_THR(x) ((x)>=(4175) ? ((x-4175)/25+0x22) : (0))///< 0x22 to 0x2E: range from 4175 mV to 4475 mV,else 2700mV
#define UV_THR(x) ((x)>=(1200) ? ((x-1200)/50) : (0x28))///< 0x00 to 0x26: range from 1200 mV to 3100 mV,else 3100mV

#define MAIN_GAIN(x)		(u8)((x+0.390625f)/0.0031f)///<MAIN_ADC_GAIN的设置
#define MAIN_OFFSET(x)		(u8)((x+24.41606f)/0.19073f)///<MAIN_ADC_OFFSET的设置
#define AUX_GAIN(x)			(u8)((x+0.390625f)/0.0031f)///<MAIN_ADC_GAIN的设置
#define AUX_OFFSET(x)		(u8)((x+24.41606f)/0.19073f)///<MAIN_ADC_OFFSET的设置

/**@brief   诊断、校验宏定义
* @{
*/
#define VCCB(x)				x/10-1 //x取值是【10、20、30……160】，整数值
#define Dis_ADC_Comp		0x0	//禁止对采集信号进行比较
#define Cell_Vol_Check		0x1	//电芯电压的比较检测
#define VC_Open_Check		0x2	//VC开线检测
#define CB_Open_Check		0x3	//CB开线检测
#define CBFET_Check			0x4	//FET检测
#define GPIO_Check			0x5	//GPIO检测

#define TEMP(x)				x/2-1	//x的取值是【2%，4%...16%】，对应寄存器0~7
#define OW(x)				x/250-1 //x的取值是250mV-4000mV，等差250mV

#define SINK_ALL_OFF		0x0	//全部关闭
#define SINK_VC				0x1	//开启VC通道
#define SINK_CB				0x2	//开启CB通道
#define SINK_BB				0x3	//开启BBP和BBN通道
/**@} */

#define BAL_DUTY_5S 		0x00 //5s  Selection is sampled whenever [BAL_GO] = 1
#define BAL_DUTY_10S 		0x01 //
#define BAL_DUTY_30S 		0x02 //
#define BAL_DUTY_60S 		0x03 //
#define BAL_DUTY_5MIN 		0x04 //
#define BAL_DUTY_10MIN	 	0x05 //
#define BAL_DUTY_20MIN		0x06 //
#define BAL_DUTY_30MIN		0x07 //

#define BAL_ACT_NOACTION	0x0	//No action
#define BAL_ACT_ENSLP		0x1	//Enters SLEEP
#define BAL_ACT_ENSTDO		0x2	//Enters SHUTDOWN

#define OVUV_DIS   			0x0 //Do not run OV and UV comparators
#define OVUV_RUN_ROUND   	0x1 //Run the OV and UV round robin with all active cells
#define OVUV_RUN_BIST	    0x2 //Run the OV and UV BIST cycle.
#define OVUV_LOCK_SINGLE  	0x3 //Lock OV and UV comparators to a single channel configured by [OVUV_LOCK3:0]

#define OVUV_LOCK(x)			(x-1)	//1:CELL1

#define OTUT_DIS   			0x00 //Do not run OT and UT comparators
#define OTUT_RUN_ROUND    	0x01 //Run the OT and UT round robin with all active cells
#define OTUT_RUN_BIST	    0x02 //Run the OT and UT BIST cycle.
#define OTUT_LOCK_SINGLE  	0x03 //Lock OT and UT comparators to a single channel configured by [OTUT_LOCK3:0]

#define OTUT_LOCK(x)		(x-1)	//1:GPIO1

#define GPIO_HIHG_Z			000B	//As disabled, high-Z
#define GPIO_ADC_OUTPUT		001B	//As ADC and OTUT inputs
#define GPIO_ADC_ONLY		001B	//As ADC only input
#define GPIO_DIG_INPUT		001B	//As digital input
#define GPIO_HIGH_OUTPUT  	001B	//As output high
#define GPIO_LOW_OUTPUT		001B	//As output low

#define SPI_NUMBIT_24		0	//24bit
#define SPI_NUMBIT_8		8	//8bit
#define SPI_NUMBIT_16		16	//16bit

#define MARGIN_Normal_Read		0//
#define MARGIN_Margin_1_Read	2//
/**@} */

/**@name    寄存器声明
* @{
*/
typedef struct _Bq_Register_Group
{
	union
	{
		struct
		{
			u8 ADDRESS			:6; //This register shows the default device address used when [DIR_SEL] = 0,and programmed in the OTP
			u8 SPARE			:2; //spare
		}Bit;
		u8 Byte;
	}DIR0_ADDR_OTP;
	
	union
	{
		struct
		{
			u8 ADDRESS			:6; //This register shows the default device address used when [DIR_SEL] = 1,and programmed in the OTP
			u8 SPARE			:2; //spare
		}Bit;
		u8 Byte;
	}DIR1_ADDR_OTP;
	
	union
	{
		struct
		{
			u8 ADDRESS			:6; //Always shows the current device address used by the device when [DIR_SEL] = 0,can be write
			u8 SPARE			:2; //spare
		}Bit;
		u8 Byte;
	}DIR0_ADDR;
	
	union
	{
		struct
		{
			u8 ADDRESS			:6; //Always shows the current device address used by the device when [DIR_SEL] = 1,can be write
			u8 SPARE			:2; //spare
		}Bit;
		u8 Byte;
	}DIR1_ADDR;

	u8 PARTID;	//Device revision 0x00 = Revision A1 0x01 to 0xFF = Reserved
	u8 DIE_ID1;	//Die ID for TI factory use
	u8 DIE_ID2;	//Die ID for TI factory use
	u8 DIE_ID3;	//Die ID for TI factory use
	u8 DIE_ID4;	//Die ID for TI factory use
	u8 DIE_ID5;	//Die ID for TI factory use
	u8 DIE_ID6;	//Die ID for TI factory use
	u8 DIE_ID7;	//Die ID for TI factory use
	u8 DIE_ID8;	//Die ID for TI factory use
	u8 DIE_ID9;	//Die ID for TI factory use		
		
	u8 CUST_MISC1;	//Customer scratch pad
	u8 CUST_MISC2;	//Customer scratch pad
	u8 CUST_MISC3;	//Customer scratch pad
	u8 CUST_MISC4;	//Customer scratch pad
	u8 CUST_MISC5;	//Customer scratch pad
	u8 CUST_MISC6;	//Customer scratch pad
	u8 CUST_MISC7;	//Customer scratch pad
	u8 CUST_MISC8;	//Customer scratch pad
		
	union
	{
		struct
		{
			u8 HB_EN			:1; //Enables HEARTBEAT transmitter when device is in SLEEP mode.0 disable;1 enable
			u8 FTONE_EN			:1; //Enables FAULT TONE transmitter when device is in SLEEP mode.0 disable;1 enable
			u8 NFAULT_EN		:1; //Enables the NFAULT function. 0:pulled up; 1:pulled low to indicate an unmasked fault is detected
			u8 TWO_STOP_EN		:1; //UART ,0 = One STOP bit,1=TWO
			u8 FCOMM_EN			:1; //Enables the fault state detection through communication in ACTIVE mode.0 disable;1 enable
			u8 MULTIDROP_EN		:1; //0 Daisy chain of base device ; 1 Multidrop(standalone)
			u8 NO_ADJ_CB		:1; //0  allow two adjacent CB FETs;1 not allow
			u8 SPARE			:1; //spare
		}Bit;
		u8 Byte;
	}DEV_CONF;	
	
	union
	{
		struct
		{
			u8 NUM_CELL			:4; //0x0 = 6S,0x1=7S....
			u8 SPARE			:4; //spare
		}Bit;
		u8 Byte;
	}ACTIVE_CELL;
	
/*
*	Among the active cells specified by the ACTIVE_CELL register, this register indicates which active channel is
	excluded from the OV, UV, and VCB_DONE monitoring.
*	bus bar
*0 = No special handling of the functions mentioned above
*1 = Special handling of the functions mentioned above.
*/
	union
	{
		struct
		{
			u8 CELL9			:1; 
			u8 CELL10			:1; 
			u8 CELL11			:1; 
			u8 CELL12			:1; 
			u8 CELL13			:1; 
			u8 CELL14 			:1; 
			u8 CELL15			:1; 
			u8 CELL16			:1; 
		}Bit;
		u8 Byte;
	}BB_POSN1;	
	
	union
	{
		struct
		{
			u8 SLP_TIME			:3; //A timeout in SLEEP mode. 
			u8 TWARN_THR		:2; //Sets the TWARN threshold  T warning
			u8 SPARE			:3; 
		}Bit;
		u8 Byte;
	}PWR_TRANSIT_CONF;	
	
	
	union
	{
		struct
		{
			u8 CELL1			:1; 
			u8 CELL2			:1; 
			u8 CELL3			:1; 
			u8 CELL4			:1; 
			u8 CELL5			:1; 
			u8 CELL6 			:1; 
			u8 CELL7			:1; 
			u8 CELL8			:1; 
		}Bit;
		u8 Byte;
	}BB_POSN2;	
	
	union
	{
		struct
		{
			u8 CTL_TIME			:3; //Sets the short communication timeout
			u8 CTL_ACT			:1; //Configures the device action when long communication timeout timer expires.
			u8 CTS_TIME			:3; //Sets the long communication timeout.
			u8 SPARE			:1; //			
		}Bit;
		u8 Byte;
	}COMM_TIMEOUT_CONF;
	
	u8 TX_HOLD_OFF;	//between receive stop bit to tx
		
	union
	{
		struct
		{
			u8 TOP_STACK		:1; //Defines device as highest addressed device in the stack
			u8 STACK_DEV		:1; //Defines device as a base or stack device in daisy chain configuration.
			u8 SPARE			:6; //			
		}Bit;
		u8 Byte;
	}COMM_CTRL;
	
	union
	{
		struct
		{
			u8 ADDR_WR			:1; //Enables device to start auto-addressing.
			u8 SOFT_RESET		:1; //Resets the digital to OTP default. Bit is cleared on read.
			u8 GOTO_SLEEP		:1; //Transitions device to SLEEP mode. Bit is cleared on read.		
			u8 GOTO_SHUTDOWN	:1; //Transitions device to SHUTDOWN mode. Bit is cleared on read
			u8 SEND_SLPTOACT	:1; //Sends SLEEPtoACTIVE tone up the stack. Bit is cleared on read.
			u8 SEND_WAKE		:1; //Sends WAKE tone to next device up the stack. Bit is cleared on read.
			u8 SEND_SHUTDOWN	:1;	//Sends SHUTDOWN tone to next device up the stack.
			u8 DIR_SEL			:1; //Selects daisy chain communication direction.
		}Bit;
		u8 Byte;
	} CONTROL1;
	
	union
	{
		struct
		{
			u8 TSREF_EN			:1; //Enables TSREF LDO output. Used to bias NTC thermistor.
			u8 SEND_HW_RESET	:1; //Sends HW_RESET tone up the stack. Bit is cleared on read.
			u8 SPARE			:6; //
		}Bit;
		u8 Byte;
	} CONTROL2;
	
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}CUST_CRC;	// host-calculated CRC for customer OTP space.
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}CUST_CRC_RSLT;	//the device-calculated CRC for customer OTP space
	
	
	union
	{
		struct
		{
			u8 DRDY_BIST_PWR		:1; //Indicates the status of the power supplies diagnostic
			u8 DRDY_BIST_OVUV		:1; //Indicates the status of the OVUV protector diagnostic.
			u8 DRDY_BIST_OTUT		:1; //Indicates the status of the OTUT protector diagnostic
			u8 DRDY_OVUV			:1; //Indicates the OVUV round robin has at least run once
			u8 DRDY_OTUT			:1; //Indicates the OTUT round robin has run at least once.
			u8 SPARE 				:3;  
		}Bit;
		u8 Byte;
	}DIAG_STAT;
	
	union
	{
		struct
		{
			u8 DRDY_MAIN_ADC		:1; //Device has completed at least a single measurement on all Main ADC
			u8 DRDY_AUX_MISC		:1; //Device has completed at least a single measurement on all AUX ADC MISC
			u8 DRDY_AUX_CELL		:1; //Device has completed at least a single measurement on all AUXCELL
			u8 DRDY_AUX_GPIO		:1; //AUX ADC has completed at least a single measurement on all active GPIO
			u8 SPARE 				:4;  
		}Bit;
		u8 Byte;
	}ADC_STAT1;
	
	union
	{
		struct
		{
			u8 DRDY_VCCB			:1; //Device has finished VCELL vs. AUXCELL diagnostic comparison
			u8 DRDY_CBFET			:1; //Device has finished CB FET diagnostic comparison
			u8 DRDY_CBOW			:1; //Device has finished CB OW diagnostic comparison
			u8 DRDY_VCOW			:1; //Device has finished VC OW diagnostic comparison
			u8 DRDY_GPIO 			:1; //Device has finished the GPIO Main and AUX ADC diagnostic comparisons
			u8 DRDY_LPF				:1; //Device has finished at least 1 round of LPF checks
			u8 SPARE 				:2;  
		}Bit;
		u8 Byte;
	}ADC_STAT2;
	
	union
	{
		struct
		{
			u8 GPIO1				:1; //When GPIO is configured as digital input or output, this register shows the GPIO status
			u8 GPIO2				:1; 
			u8 GPIO3				:1; 
			u8 GPIO4				:1; 
			u8 GPIO5 				:1; 
			u8 GPIO6				:1; 
			u8 GPIO7 				:1;  
			u8 GPIO8 				:1;  
		}Bit;
		u8 Byte;
	}GPIO_STAT;
	
	union
	{
		struct
		{
			u8 CB_DONE				:1; //Indicates all cell balancing is completed
			u8 MB_DONE				:1; //Indicates module balancing is completed
			u8 ABORTFLT				:1; //Indicates cell balancing is aborted due to detection of unmasked fault.
			u8 CB_RUN				:1; //Indicates cell balancing is running
			u8 MB_RUN 				:1; //Indicates module balancing, controlled by the device, is running
			u8 CB_INPAUSE			:1; //Indicates the cell balancing pause status
			u8 OT_PAUSE_DET			:1; //Indicates the OTCB is detected if [OTCB_EN] = 1 
			u8 INVALID_CBCONF		:1; //Indicates CB is unable to start (after [BAL_GO] = 1) due to improper CB control settings. 
		}Bit;
		u8 Byte;
	}BAL_STAT;
	
	union
	{
		struct
		{
			u8 MAIN_RUN				:1; //Shows the status of the Main ADC.
			u8 AUX_RUN				:1; //Shows the status of the AUX ADC
			u8 RSVD					:1; 
			u8 OVUV_RUN				:1; //Shows the status of the OVUV protector comparators
			u8 OTUT_RUN				:1; //Shows the status of the OTUT protector comparators.
			u8 CUST_CRC_DONE		:1; //Indicates module balancing, controlled by the device, is running
			u8 FACT_CRC_DONE		:1; //Indicates the status of the factory CRC state machine.
			u8 SPARE				:1;  
		}Bit;
		u8 Byte;
	}DEV_STAT;
	
	union
	{
		struct
		{
			u8 LPF_VCELL			:3; //Configures the post ADC low-pass filter cut-off frequency for VCELL measurement
			u8 LPF_BB				:3; //Configures the post ADC low-pass filter cut-off frequency for bus bar measurement
			u8 AUX_SETTLE			:2; //The AUXCELL configures the AUX CELL settling time
		}Bit;
		u8 Byte;
	}ADC_CONF1;

	
	union
	{
		struct
		{
			u8 ADC_DLY  			:6; //If [MAIN_GO] bit is written to 1, bit Main ADC is delayed for this setting time before being enabled to start the conversion.
			u8 SPARE				:2; 
		}Bit;
		u8 Byte;
	}ADC_CONF2;

	u8  MAIN_ADC_GAIN;		//Main ADC 25C gain calibration result
	u8  MAIN_ADC_OFFSET;	//Main ADC 25C offset calibration result.
	u8  AUX_ADC_GAIN;		//8-bit register for AUX ADC gain correction.
	u8  AUX_ADC_OFFSET;		//8-bit register for AUX ADC offset correction
	

	union
	{
		struct
		{
			u8 MAIN_MODE			:2; //Sets the Main ADC run mode.
			u8 MAIN_GO				:1; //Starts main ADC conversion.
			u8 LPF_VCELL_EN			:1; //Enables digital low-pass filter post-ADC conversion
			u8 LPF_BB_EN			:1; //Enables digital low-pass filter post-ADC conversion
			u8 SPARE				:3;  
		}Bit;
		u8 Byte;
	}ADC_CTRL1;
	
	union
	{
		struct
		{
			u8 AUX_CELL_SEL			:5; //Selects which AUXCELL channel(s) will be multiplexed through the AUX ADC.
			u8 SPARE				:3;  
		}Bit;
		u8 Byte;
	}ADC_CTRL2;
	
	union
	{
		struct
		{
			u8 AUX_MODE				:2; //Sets the Main ADC run mode
			u8 AUX_GO				:1; //Starts AUX ADC conversion
			u8 AUX_GPIO_SEL			:4; //Selects which GPIO channel(s) will be multiplexed 
			u8 SPARE				:1;  
		}Bit;
		u8 Byte;
	}ADC_CTRL3;
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}VCELL[16];
	
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}BUSBAR;
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}TSREF;
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}GPIO[8];
	
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}DIETEMP[2];
	
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}AUX_CELL;
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}AUX_GPIO;
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}AUX_BAT;
	
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}AUX_REFL;
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}AUX_VBG2;
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}AUX_LPBG5;
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}AUX_AVAO_REF;
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}AUX_AVDD_REF;
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}AUX_OV_DAC;
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}AUX_UV_DAC;
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}AUX_OT_OTCB_DAC;
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}AUX_UT_DAC;
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}AUX_VCBDONE_DAC;
	
	union
	{
		struct
		{
			u8 HI;
			u8 LO;
		}Byte;
		u16 Word;
	}AUX_VCM[2];
		
	union
	{
		struct
		{
			u8 TIME					:5; //Sets the timer for cell* balancing
			u8 SPARE				:3;  
		}Bit;
		u8 Byte;
	}CB_CELL_CTRL[16];
	
	union
	{
		struct
		{
			u8 MB_THR				:6; //If MB_TIMER_CTRL is not 0x00 and BAT voltage is less than this threshold, the module balancing through GPIO3 stops
			u8 SPARE				:2;  
		}Bit;
		u8 Byte;
	}VMB_DONE_THRESH;
	
	union
	{
		struct
		{
			u8 TIME					:5; //If MB_TIMER_CTRL is not 0x00 and BAT voltage is less than this threshold, the module balancing through GPIO3 stops
			u8 SPARE				:3;  
		}Bit;
		u8 Byte;
	}MB_TIMER_CTRL;
	
	union
	{
		struct
		{
			u8 TIME					:5; //If a cell voltage is less than this threshold, the cell balancing on that cell stops.
			u8 SPARE				:3;  
		}Bit;
		u8 Byte;
	}VCB_DONE_THRESH;
	
	union
	{
		struct
		{
			u8 OTCB_THR				:5; //Sets the OTCB threshold when BAL_CTRL1[OTCB_EN] = 1
			u8 COOLOFF				:3; //Sets the COOLOFF hysteresis
			u8 SPARE				:1;  
		}Bit;
		u8 Byte;
	}OTCB_THRESH;
	
	union
	{
		struct
		{
			u8 DUTY					:3; //Selection is sampled whenever [BAL_GO] = 1 is set by the host MCU.
			u8 SPARE				:5;  
		}Bit;
		u8 Byte;
	}BAL_CTRL1;
	
	union
	{
		struct
		{
			u8 AUTO_BAL				:1; //Selects between auto or manual cell balance control.
			u8 BAL_GO				:1; //Starts cell or module balancing.
			u8 BAL_ACT				:2; //Controls the device action when the MB and CB are completed
			u8 OTCB_EN				:1; //Enables the OTCB detection during cell balancing
			u8 FLTSTOP_EN			:1; //Stops cell or module balancing if unmasked fault occurs
			u8 CB_PAUSE				:1; //Pauses cell balancing on all cells to allow diagnostics to run
			u8 SPARE				:1;
		}Bit;
		u8 Byte;
	}BAL_CTRL2;
	
	u8 CB_COMPLETE1;	//Cell balance completion for cell9 to cell16.
	u8 CB_COMPLETE2;  //Cell balance completion for cell1 to cell8. 
	
	union
	{
		struct
		{
			u8 OV_THR				:6; //Sets the overvoltage threshold for the OV comparator
			u8 SPARE				:2; 
		}Bit;
		u8 Byte;
	}OV_THRESH;			//alone function
	
	union
	{
		struct
		{
			u8 UV_THR				:6; //Sets the undervoltage threshold for the UV comparator.
			u8 SPARE				:2; 
		}Bit;
		u8 Byte;
	}UV_THRESH;		//alone function
	
	union
	{
		struct
		{
			u8 OT_THR				:5; //Sets the OT threshold for the OT comparator.
			u8 UT_THR				:3; //Sets the UT threshold for the UT comparator
		}Bit;
		u8 Byte;
	}OTUT_THRESH;
	
	union
	{
		struct
		{
			u8 OVUV_MODE			:2; //Sets the OV and UV comparators operation mode when [OVUV_GO] = 1
			u8 OVUV_GO				:1; //Starts the OV and UV comparators.
			u8 OVUV_LOCK			:4; //Configures a particular single channel as the OV and UV comparators input when [OVUV_MOD1:0] = 0b11
			u8 VCBDONE_THR_LOCK		:1;	//As the UV comparator is switching between UV threshold and VCBDONE threshold to measure the UV DAC or the VCBDONE DAC result for diagnostics
		}Bit;
		u8 Byte;
	}OVUV_CTRL;
	
	union
	{
		struct
		{
			u8 OTUT_MODE			:2; //Sets the OT and UT comparators operation mode when [OTUT_GO] = 1
			u8 OTUT_GO				:1; //Starts the OT and UT comparators
			u8 OTUT_LOCK			:4; //Configures a particular single channel as the OT and UT comparators input when [OTUT_MOD1:0] = 0b11.
			u8 OTCB_THR_LOCK		:1; //As the OT comparator is switching between OT threshold and OTCB threshold to measure the OT or OTCB
			u8 SPARE				:1; 
		}Bit;
		u8 Byte;
	}OTUT_CTRL;
	
	union
	{
		struct
		{
			u8 GPIO1				:3; //Configures GPIO1.
			u8 GPIO2				:3; //Configures GPIO2.
			u8 SPI_EN				:1; //Enables SPI master on GPIO4, GPIO5 and GPIO6, GPIO7
			u8 FAULT_IN_EN			:1; //Enables GPIO8 as an active-low input to trigger the NFAULT pin when the input signal is low.
		}Bit;
		u8 Byte;
	}GPIO_CONF1;
	
	union
	{
		struct
		{
			u8 GPIO3				:3; //Configures GPIO3.
			u8 GPIO4				:3; //Configures GPIO4.
			u8 RSVD					:1; 
			u8 SPARE				:1; 
		}Bit;
		u8 Byte;
	}GPIO_CONF2;
	
	union
	{
		struct
		{
			u8 GPIO5				:3; //Configures GPIO5.
			u8 GPIO6				:3; //Configures GPIO6.
			u8 RSVD					:1; 
			u8 SPARE				:1; 
		}Bit;
		u8 Byte;
	}GPIO_CONF3;
	
	union
	{
		struct
		{
			u8 GPIO7				:3; //Configures GPIO7.
			u8 GPIO8				:3; //Configures GPIO8.
			u8 RSVD					:1; 
			u8 SPARE				:1; 
		}Bit;
		u8 Byte;
	}GPIO_CONF4;
	
	
	union
	{
		struct
		{
			u8 NUMBIT				:5; //SPI transaction length.
			u8 CPHA					:1; //Sets the edge of SCLK where data is sampled on MISO.
			u8 CPOL					:1; //Sets the SCLK polarity.
			u8 SPARE				:1; 
		}Bit;
		u8 Byte;
	}SPI_CONF;
	
	union
	{
		struct
		{
			u8 SPI_GO				:1; //Executes the SPI transaction. T
			u8 SS_CTRL				:1; //Programs the state of SS
			u8 SPARE				:6; 
		}Bit;
		u8 Byte;
	}SPI_EXE;
	
	u8 SPI_TX[3];	//Data to be used to write to SPI slave device.
	u8 SPI_RX[3];	//Data returned from a read during SPI transaction.
	
	union
	{
		struct
		{
			u8 MARGIN_GO			:1; //Starts OTP Margin test set by the [MARGIN_MOD] bit.
			u8 MARGIN_MODE			:3; //Configures OTP Margin read mode:
			u8 FLIP_FACT_CRC		:1; //An enable bit to flip the factory CRC value.
			u8 SPARE				:4; 
		}Bit;
		u8 Byte;
	}DIAG_OTP_CTRL;
	
	union
	{
		struct
		{
			u8 FLIP_TR_CRC			:1; //Sends a purposely incorrect communication (during transmitting response) CRC by inverting all of the calculated CRC bits..
			u8 SPI_LOOPBACK			:1; //Enables SPI loopback function to verify SPI functionality
			u8 SPARE				:6; 
		}Bit;
		u8 Byte;
	}DIAG_COMM_CTRL;
	
	union
	{
		struct
		{
			u8 PWR_BIST_GO			:1; //When written to 1, the power supply BIST diagnostic will start. 
			u8 BIST_NO_RST			:1; //Use for further diagnostic if the power supply BIST detects a failure
			u8 SPARE				:6; 
		}Bit;
		u8 Byte;
	}DIAG_PWR_CTRL;
	
	u8 DIAG_CBFET_CTRL1;	//Enables CBFET for CBFET diagnostic CELL16-9
	u8 DIAG_CBFET_CTRL2;	//Enables CBFET for CBFET diagnostic CELL8-1
	
	union
	{
		struct
		{
			u8 BB_THR			:3; //Additional delta value added to the VCCB_THR setting,
			u8 GPIO_THR			:3; //Configures the GPIO comparison delta threshold between Main and AUX ADC measurements
			u8 SPARE			:2; 
		}Bit;
		u8 Byte;
	}DIAG_COMP_CTRL1;
	
	union
	{
		struct
		{
			u8 OW_THR			:4; //Configures the OW detection threshold for diagnostic comparison.
			u8 VCCB_THR			:4; //Configures the VCELL vs. AUXCELL delta. The VCELL vs. AUXCELL check is considered pass
		}Bit;
		u8 Byte;
	}DIAG_COMP_CTRL2;
	
	union
	{
		struct
		{
			u8 COMP_ADC_GO		:1; //Device starts diagnostic test specified by [COMP_ADC_SEL2:0] setting. 
			u8 COMP_ADC_SEL		:3; //Enables the device diagnostic comparison
			u8 OW_SNK			:2; //Turns on current sink on VC pins, CB pins, or BBP/N pins.
			u8 EXTD_CBFET   	:1; //When CBFET check comparison is selected, [COMP_ADC_SEL2:0] = 0b101, device turns off all CBFET upon
																//the completion of the comparison. If this bit is set to 1, the device will put the CBFET check in an extended mode
																//in which the device will NOT turn off the CBFETs.
			u8 SPARE			:1;
		}Bit;
		u8 Byte;
	}DIAG_COMP_CTRL3;
	
	union
	{
		struct
		{
			u8 LPF_FAULT_INJ	:1; //Injects fault condition to the diagnostic LPF during LPF diagnostic
			u8 COMP_FAULT_INJ	:1; //Injects fault to the ADC comparison logic.
			u8 SPARE			:6;
		}Bit;
		u8 Byte;
	}DIAG_COMP_CTRL4;
	
	union
	{
		struct
		{
			u8 PROT_BIST_NO_RST		:1; //Use for further diagnostic if the protector BIST detects a failure
			u8 SPARE				:7;
		}Bit;
		u8 Byte;
	}DIAG_PROT_CTRL;
	
	union
	{
		struct
		{
			u8 MSK_PWR				:1; //To mask the NFAULT assertion from any FAULT_PWR1 to FAULT_PWR3 register bit
			u8 MSK_SYS				:1;	//To mask the NFAULT assertion from any FAULT_SYS register bit.
			u8 MSK_COMP				:1; //Masks the FAULT_COMP_* registers to trigger NFAULT
			u8 MSK_OV				:1; //Masks the FAULT_OV* registers to trigger NFAULT
			u8 MSK_UV				:1; //Masks the FAULT_UV* registers to trigger NFAULT
			u8 MSK_OT				:1; //Masks the FAULT_OT* registers to trigger NFAULT.
			u8 MSK_UT				:1; //Masks the FAULT_UT* registers to trigger NFAULT.
			u8 MSK_PROT				:1; //Masks the FAULT_PROT* registers to trigger NFAULT
		}Bit;
		u8 Byte;
	}FAULT_MSK1;
	
	union
	{
		struct
		{
			u8 MSK_COMM1			:1; //Masks FAULT_COMM1 register on NFAULT triggering.
			u8 MSK_COMM2			:1;	//Masks FAULT_COMM2 register on NFAULT triggering
			u8 MSK_COMM3_HB			:1; //Masks FAULT_COMM3[HB_FAST] or [HB_FAIL] faults on NFAULT triggering.
			u8 MSK_COMM3_FTONE		:1; //Masks FAULT_COMM3[FTONE_DET] fault on NFAULT triggering.
			u8 MSK_COMM3_FCOMM		:1; //Masks FAULT_COMM3[FCOMM_DET] fault on NFAULT triggering
			u8 MSK_OTP_DATA			:1; //Masks the FAULT_OTP register (all bits except [CUST_CRC] and [FACT_CRC]) on NFAULT triggering
			u8 MSK_OTP_CRC			:1; //Masks the FAULT_OTP register ([CUST_CRC] and [FACT_CRC] only) on NFAULT triggering.
			u8 SPARE				:1; 
		}Bit;
		u8 Byte;
	}FAULT_MSK2;
	
	union
	{
		struct
		{
			u8 RST_PWR				:1; //To reset the FAULT_PWR1 to FAULT_PWR3 registers to 0x00
			u8 RST_SYS				:1;	//To reset the FAULT_SYS register to 0x00
			u8 RST_COMP				:1; //Resets all FAULT_COMP_* registers to 0x00.
			u8 RST_OV				:1; //Resets all FAULT_OV* registers to 0x00
			u8 RST_UV				:1; //Resets all FAULT_UV* registers to 0x00
			u8 RST_OT				:1; //Resets all FAULT_OT registers to 0x00
			u8 RST_UT				:1; //Resets all FAULT_UT registers to 0x00
			u8 RST_PROT				:1; //Resets the FAULT_PROT1 and FAULT_PROT2 registers to 0x00.
		}Bit;
		u8 Byte;
	}FAULT_RST1;
	
	union
	{
		struct
		{
			u8 RST_COMM1			:1; //Resets FAULT_COMM1 and DEBUG_COMM_UART* registers.
			u8 RST_COMM2			:1;	//Resets FAULT_COMM2, DEBUG_COML*, and DEBUG_COMM_COMH* registers
			u8 RST_COMM3_HB			:1; //Resets FAULT_COMM3[HB_FAST] and [HB_FAIL] bits.
			u8 RST_COMM3_FTONE		:1; //Resets FAULT_COMM3[FTONE_DET].
			u8 RST_COMM3_FCOMM		:1; //Resets FAULT_COMM3[FCOMM_DET]
			u8 RST_OTP_DATA			:1; //Resets the FAULT_OTP register ([SEC_DETECT] and [DED_DETECT] only).
			u8 RST_OTP_CRC			:1; //Resets the FAULT_OTP register ([CUST_CRC] and [FACT_CRC] only).
			u8 RSVD					:1; 
		}Bit;
		u8 Byte;
	}FAULT_RST2;
	
	union
	{
		struct
		{
			u8 FAULT_PWR			:1; //This bit is set if [MSK_PWR] = 0 and any of the FAULT_PWR1 to FAULT_PWR3 register bits is set.
			u8 FAULT_SYS			:1;	//This bit is set if [MSK_SYS] = 0 and any of the FAULT_SYS1 register bits is set
			u8 FAULT_OVUV			:1; //This bit is set if any of the following is true:
			u8 FAULT_OTUT			:1; //
			u8 FAULT_COMM			:1; //
			u8 FAULT_OTP			:1; //This bit is set if [MSK_OTP] = 0 and any of the FAULT_OTP register bits is set.
			u8 FAULT_COMP_ADC		:1; //Resets the FAULT_OTP register ([CUST_CRC] and [FACT_CRC] only).
			u8 FAULT_PROT			:1; //This bit is set if [MSK_PROT] = 0 and any of the FAULT_PROT1 or FAULT_PROT2 register bits is set.
		}Bit;
		u8 Byte;
	}FAULT_SUMMARY;
	
	union
	{
		struct
		{
			u8 STOP_DET				:1; //Indicates an unexpected STOP condition is received.
			u8 COMMCLR_DET			:1;	//A UART communication clear signal is detected
			u8 UART_RC				:1; //Indicates a UART FAULT is detected during receiving a command frame
			u8 UART_RR				:1; //Indicates a UART FAULT is detected when receiving a response frame
			u8 UART_TR				:1; //Indicates a UART FAULT is detected when transmitting a response frame.
			u8 RSVD					:3; 
		}Bit;
		u8 Byte;
	}FAULT_COMM1;
	
	union
	{
		struct
		{
			u8 COMH_BIT				:1; //Indicates a COMH bit level fault is detected
			u8 COMH_RC				:1;	//Indicates a COMH byte level fault is detected
			u8 COMH_RR				:1; //Indicates a COMH byte level fault is detected when receiving a response frame
			u8 COMH_TR				:1; //Indicates a COMH byte level fault is detected when transmitting a response frame
			u8 COML_BIT				:1; //Indicates a COML bit level fault is detected which would cause at least one byte level fault.
			u8 COML_RC				:1; //Indicates a COML byte level fault is detected when receiving a command frame
			u8 COML_RR				:1; //Indicates a COML byte level fault is detected when receiving a response frame
			u8 COML_TR				:1; //Indicates a COML byte level fault is detected when transmitting a response frame
		}Bit;
		u8 Byte;
	}FAULT_COMM2;
	
	union
	{
		struct
		{
			u8 HB_FAST				:1; //Indicates HEARTBEAT is received too frequently
			u8 HB_FAIL				:1;	//Indicates HEARTBEAT is not received within an expected time
			u8 FTONE_DET			:1; //Indicates a FAULT TONE is received
			u8 FCOMM_DET			:1; //Received communication transaction with the Fault Status bits set by any of the upper stack device
			u8 RSVD					:4; 
		}Bit;
		u8 Byte;
	}FAULT_COMM3;
	
	union
	{
		struct
		{
			u8 GBLOVERR				:1; //Indicates that on overvoltage error is detected on one of the OTP pages.
			u8 FACTLDERR			:1; //Indicates errors during the factory space OTP load process.
			u8 CUSTLDERR			:1;	//Indicates errors during the customer space OTP load process
			u8 FACT_CRC				:1; //Indicates a CRC error has occurred in the factory register space.
			u8 CUST_CRC				:1; //Indicates a CRC error has occurred in the customer register space
			u8 SEC_DET				:1; //Indicates a SEC error has occurred during the OTP load.
			u8 DED_DET				:1; //Indicates a DED error has occurred during the OTP load
			u8 RSVD					:1; 
		}Bit;
		u8 Byte;
	}FAULT_OTP;
	
	union
	{
		struct
		{
			u8 TWARN				:1; //Indicates the die temperature (die temp 2) is higher than the TWARN_THR[1:0] setting
			u8 TSHUT				:1; //Indicates the previous shutdown was a thermal shutdown,
			u8 CTS					:1;	//Indicates a short communication timeout occurred.
			u8 CTL					:1; //Indicates a long communication timeout occurred
			u8 DRST					:1; //Indicates a digital reset has occurred
			u8 GPIO					:1; //Indicates GPIO8 detects a FAULT input when GPIO_CONF1[FAULT_IN_EN] = 1.
			u8 SHUTDOWN_REC			:1; //Indicates the previous device shutdown was caused by one of the following:
			u8 LFO					:1; //Indicated LFO frequency is outside an expected range
		}Bit;
		u8 Byte;
	}FAULT_SYS;
	
	union
	{
		struct
		{
			u8 VPARITY_FAIL			:1; //Indicates a parity fault is detected on any of the following OVUV related configurations
			u8 TPARITY_FAIL			:1; //Indicates a parity fault is detected on any of the following OTUT related configurations
			u8 RSVD					:6;	
		}Bit;
		u8 Byte;
	}FAULT_PROT1;
	
	union
	{
		struct
		{
			u8 UVCOMP_FAIL			:1; //Indicates the UV comparator fails during BIST test
			u8 OVCOMP_FAIL			:1; //Indicates the OV comparator fails during BIST test.
			u8 OTCOMP_FAIL			:1;	//Indicates the OT comparator fails during BIST test
			u8 UTCOMP_FAIL			:1; //Indicates the UT comparator fails during BIST test.
			u8 VPATH_FAIL			:1; //Indicates a fault is detected along the OVUV signal path during BIST test
			u8 TPATH_FAIL			:1; //Indicates a fault is detected along the OTUT signal path during BIST test
			u8 BIST_ABORT			:1; //Indicates either OVUV or OTUT BIST run is aborted
			u8 RSVD					:1; 
		}Bit;
		u8 Byte;
	}FAULT_PROT2;
	
	u8 FAULT_OV1;					//OV9_DET to OV16_DET = OV fault status
	u8 FAULT_OV2;					//OV1_DET to OV8_DET = OV fault status
	u8 FAULT_UV1;					//UV9_DET to UV16_DET = UV fault status
	u8 FAULT_UV2;					//UV1_DET to UV8_DET = UV fault status
	u8 FAULT_OT;					//OT1_DET to OT8_DET = OT fault status
	u8 FAULT_UT;					//UT1_DET to UT8_DET = UT fault status
	u8 FAULT_COMP_GPIO;				//Indicates ADC vs. AUX ADC GPIO measurement diagnostic results for GPIO1 to GPIO8.
	u8 FAULT_COMP_VCCB1;			//Indicates voltage diagnostic results for cell9 to cell16.
	u8 FAULT_COMP_VCCB2;			//Indicates voltage diagnostic results for cell1 to cell8.
	u8 FAULT_COMP_VCOW1;			//Indicates VC OW diagnostic results for cell9 to cell 16.
	u8 FAULT_COMP_VCOW2;			//Indicates VC OW diagnostic results for cell1 to cell 8
	u8 FAULT_COMP_CBOW1;			//Results of the CB OW diagnostic for CB FET9 to CB FET16
	u8 FAULT_COMP_CBOW2;			//Results of the CB OW diagnostic for CB FET1 to CB FET8.
	u8 FAULT_COMP_CBFET1;			//Results of the CB FET diagnostic for CB FET9 to CB FET16
	u8 FAULT_COMP_CBFET2;			//Results of the CB FET diagnostic for CB FET1 to CB FET8.
		
	
	union
	{
		struct
		{
			u8 LPF_FAIL				:1; //Indicates LPF diagnostic result
			u8 COMP_ADC_ABORT		:1; //Indicates the most recent ADC comparison diagnostic is aborted due to improper setting
			u8 RSVD					:6;	
		}Bit;
		u8 Byte;
	}FAULT_COMP_MISC;
	
	
	union
	{
		struct
		{
			u8 AVDD_OV				:1; //Indicates an overvoltage fault on the AVDD LDO.
			u8 AVDD_OSC				:1; //Indicates AVDD is oscillating outside of acceptable limits.
			u8 DVDD_OV				:1;	//Indicates an overvoltage fault on the DVDD LDO
			u8 CVDD_OV				:1; //Indicates an overvoltage fault on the CVDD LDO
			u8 CVDD_UV				:1; //Indicates an undervoltage fault on the CVDD LDO
			u8 REFHM_OPEN			:1; //Indicates an open condition on REFHM pin
			u8 DVSS_OPEN			:1; //Indicates an open condition on DVSS pin
			u8 CVSS_OPEN			:1; //Indicates an open condition on CVSS pin
		}Bit;
		u8 Byte;
	}FAULT_PWR1;
	
	union
	{
		struct
		{
			u8 TSREF_OV				:1; //Indicates an overvoltage fault on the TSREF LDO.
			u8 TSREF_UV				:1; //Indicates an undervoltage fault on the TSREF LDO.
			u8 TSREF_OSC			:1;	//Indicates TSREF is oscillating outside of an acceptable limit
			u8 NEG5V_UV				:1; //Indicates an undervoltage fault on the NEG5V charge pump
			u8 REFH_OSC				:1; //Indicates REGH reference is oscillating outside of an acceptable limit.
			u8 AVAO_OV				:1; //Indicates an overvoltage fault on the AVAO_REF
			u8 PWRBIST_FAIL			:1; //Indicates a fail on the power supply BIST run
			u8 RSVD					:1; 
		}Bit;
		u8 Byte;
	}FAULT_PWR2;
	
	union
	{
		struct
		{
			u8 AVDDUV_DRST			:1; //Indicates a digital reset occurred due to AVDD UV detected.
			u8 AVDDREFUV_DRST		:1; //Indicates a digital reset occurred due to AVDDREF UV detected
			u8 AVAO_SW_FAIL			:1;	//Indicates a fault is detected on the AVAO switch.
			u8 RSVD					:5; 
		}Bit;
		u8 Byte;
	}FAULT_PWR3;
	
	
	u8 DEBUG_CTRL_UNLOCK;		//Write the unlock code (0xA5) to this register to activate the setting in the DEBUG_COMM_CTRL* register
	
	
	union
	{
		struct
		{
			u8 USER_DAISY_EN		:1; //This bit enables the debug COML and COMH control bits in the DEBUG_COMM_CTRL2 register
			u8 USER_UART_EN 		:1; //This bit enables the debug UART control bits
			u8 UART_TX_EN			:1;	//Stack device, by default, has the UART TX disabled
			u8 UART_MIRROR_EN		:1; //This bit enables the stack VIF communication to mirror to UART
			u8 UART_BAUD			:1; //This bit changes the UART baud rate to 250kb/s.
			u8 RSVD					:3; 
		}Bit;
		u8 Byte;
	}DEBUG_COMM_CTRL1;
	
	union
	{
		struct
		{
			u8 COMH_RX_EN			:1; //Enables COMH receiver.
			u8 COMH_TX_EN		 	:1; //Enables COMH transmitter
			u8 COML_RX_EN			:1;	//Enables COML receiver
			u8 COML_TX_EN			:1; //Enables COML transmitter
			u8 RSVD					:4; 
		}Bit;
		u8 Byte;
	}DEBUG_COMM_CTRL2;
	
	
	union
	{
		struct
		{
			u8 COMH_RX_ON			:1; //Shows the current COMH receiver status.
			u8 COMH_TX_ON		 	:1; //Shows the current COMH transmitter status.
			u8 COML_RX_ON			:1;	//Shows the current COML receiver status
			u8 COML_TX_ON			:1; //Shows the current COML transmitter status
			u8 HW_DAISY_DRV			:1; //Indicates the COML and COMH are controlled by the device itself or by MCU control.
			u8 HW_UART_DRV			:1;	//Indicates the UART TX is controlled by the device itself or by MCU control
			u8 RSVD					:2; 
		}Bit;
		u8 Byte;
	}DEBUG_COMM_STAT;
	
	union
	{
		struct
		{
			u8 RC_CRC				:1; //Detects a CRC error in the received command frame from UART
			u8 RC_UNEXP			 	:1; //In a stack device, it is not expected to receive a stack or broadcast command through the UART interface.
			u8 RC_BYTE_ERR			:1;	//Detects any byte error, other than the error in the initialization byte, in the received command frame
			u8 RC_SOF				:1; //Detects a start-of-frame (SOF) error
			u8 RC_TXDIS				:1; //Detects if UART TX is disabled, but the host MCU has issued a command to read data from the device.
			u8 RC_IERR				:1;	//Detects initialization byte error in the received command frame
			u8 RSVD					:2; 
		}Bit;
		u8 Byte;
	}DEBUG_UART_RC;
	
	
	union
	{
		struct
		{
			u8 RR_CRC				:1; //Detects are CRC error in the received response frame from UART
			u8 RR_BYTE_ERR	 		:1; //Detects any byte error,
			u8 RR_SOF				:1;	//Indicates a UART CLEAR is received while receiving the response frame
			u8 TR_WAIT				:1; //The device is waiting for its turn to transfer a response out but the action is terminated
			u8 TR_SOF				:1; //Indicates that a UART CLEAR is received while the device is still transmitting data
			u8 RSVD					:3; 
		}Bit;
		u8 Byte;
	}DEBUG_UART_RR_TR;
	
	union
	{
		struct
		{
			u8 BIT					:1; //The device has detected a data bit; however, 
																//the detection samples are not enough to assure a strong 1 or 0
			u8 SYNC1				:1; //Unable to detect the preamble half-bit or any of the [SYNC1:0] bits
			u8 SYNC2				:1;	//The Preamble half-bit and the [SYNC1:0] bits are detected
			u8 BERR_TAG				:1; //Set when the received communication is tagged with [BERR] = 1.
			u8 PERR					:1; //Detects abnormality of the incoming communication frame and hence
			u8 RSVD					:3; 
		}Bit;
		u8 Byte;
	}DEBUG_COMH_BIT;
	
	union
	{
		struct
		{
			u8 RC_CRC				:1; //Indicates a CRC error that resulted in one or more COMH command frames being discarded
			u8 RC_UNEXP			 	:1; //If [DIR_SEL] = 0, but device receives command frame from COMH 
																//which is an invalid condition and device will set this error bit.
			u8 RC_BYTE_ERR			:1;	//Valid when [DIR_SEL] = 1. Detected any byte error, 
																//other than the error in the initialization byte, in the received command frame
			u8 RC_SOF				:1; //Valid when [DIR_SEL] = 1. Detects a start-of-frame (SOF) error on COMH. T
			u8 RC_TXDIS				:1; //Valid when [DIR_SEL] = 1. Device detects the COMH TX is disabled but the device receives a command to read
																//data (that is, to transmit data out). The command frame will be counted as a discard frame
			u8 RC_IERR				:1; //...
			u8 RSVD					:2; 
		}Bit;
		u8 Byte;
	}DEBUG_COMH_RC;
	
	
	union
	{
		struct
		{
			u8 RR_CRC				:1; //Indicates a CRC error that resulted in one or more COMH response frames being discarded
			u8 RR_UNEXP			 	:1; //If [DIR_SEL] = 1, but device received response frame from COMH 
																//which is an invalid condition and device sets this error bit.
			u8 RR_BYTE_ERR			:1;	//Valid when [DIR_SEL] = 0. Detects any byte error, other than the error in the initialization byte, in the received
																//response frame. This error can trigger one or more error bits set in the DEBUG_COMMH_BIT register.
			u8 RR_SOF				:1; //Valid when [DIR_SEL] = 0. Detects a start-of-frame (SOF) error on COMH
			u8 RR_TXDIS				:1; //Valid when [DIR_SEL] = 0, device receives a response but fails to transmit to the next device because the COMH
																//TX is disabled. The frame is counted as a discarded frame.
			u8 TR_WAIT				:1; //The device is waiting for its turn to transfer a response out 
																//but the action is terminated because the devicereceives a new command.
			u8 RSVD					:2; 
		}Bit;
		u8 Byte;
	}DEBUG_COMH_RR_TR;
	
	
	union
	{
		struct
		{
			u8 BIT					:1; //The device has detected a data bit.
			u8 SYNC1				:1; //Unable to detect the preamble half-bit or any of the [SYNC1:0] bits. 
			u8 SYNC2				:1;	//The Preamble half-bit and the [SYNC1:0] bits are detected
			u8 BERR_TAG				:1; //Set when the received communication is tagged with BERR
			u8 PERR					:1; //Detect abnormality of the incoming communication frame 
																//and the outgoing communication frame will be set with	BERR.
			u8 RSVD					:3; 
		}Bit;
		u8 Byte;
	}DEBUG_COML_BIT;
	
	
	union
	{
		struct
		{
			u8 RC_CRC				:1; //Indicates a CRC error that resulted in one or more COML command frames being discarded.
			u8 RC_UNEXP			 	:1; //If [DIR_SEL] = 1, but device received command frame from COML which is an invalid condition 
																//and device will set this error bit.
			u8 RC_BYTE_ERR			:1;	//Valid when [DIR_SEL] = 0. Detected any byte error, 
																//other than the error in the initialization byte, in the received command frame.
			u8 RC_SOF				:1; //Valid when [DIR_SEL] = 0.
			u8 RC_TXDIS				:1; //Valid when [DIR_SEL] = 0. 
			u8 RC_IERR				:1; //Detected initialization byte error in the received command frame.
			u8 RSVD					:2; 
		}Bit;
		u8 Byte;
	}DEBUG_COML_RC;
	
	union
	{
		struct
		{
			u8 RR_CRC				:1; //Indicates a CRC error that resulted in one or more COML response frames being discarded.
			u8 RR_UNEXP			 	:1; //If [DIR_SEL] = 0, but device received a response frame from COML 
																//which is an invalid condition and device will set this error bit.
			u8 RR_BYTE_ERR			:1;	//Valid when [DIR_SEL] = 1
			u8 RR_SOF				:1; //Valid when [DIR_SEL] = 1.
			u8 RR_TXDIS				:1; //Valid when [DIR_SEL] = 1
			u8 TR_WAIT				:1; //The device is waiting for its turn to transfer a response out
																//but the action is terminated because the device receives a new command
			u8 RSVD					:2; 
		}Bit;
		u8 Byte;
	}DEBUG_COML_RR_TR;
	
	u8 DEBUG_UART_DISCARD; 		//UART frame counter to track the number of discard frames received or transmitted.
	u8 DEBUG_COMH_DISCARD;		//COMH frame counter to track the number of discard frames received or transmitted.
	u8 DEBUG_COML_DISCARD;		//COML frame counter to track the number of discard frames received or transmitted.
	u8 DEBUG_UART_VALID_HI;		//The high-byte of UART frame counter to track the number of valid frames received or transmitted.
	u8 DEBUG_UART_VALID_LO;		//The low-byte of UART frame counter to track the number of valid frames received or transmitted.
	u8 DEBUG_COMH_VALID_HI;		//The high-byte of COMH frame counter to track the number of valid frames received or transmitted.
	u8 DEBUG_COMH_VALID_LO;		//The low-byte of COMH frame counter to track the number of valid frames received or transmitted.
	u8 DEBUG_COML_VALID_H;		//The high-byte of COML frame counter to track the number of valid frames received or transmitted.
	u8 DEBUG_COML_VALID_LO;		//The low-byte of COML frame counter to track the number of valid frames received or transmitted
	u8 DEBUG_OTP_SEC_BLK;		//Holds last OTP block address where SEC occurred. Valid only when FAULT_OTP[SEC_DET] = 1.
	u8 OTP_PROG_UNLOCK1[4];		//programming unlock code is required as part of the OTP programming unlock sequence
								//before performing OTP programming
	u8 OTP_PROG_UNLOCK2[4]; 	//OTP programming unlock code, required as part of the OTP programming unlock sequence
								//before performing OTP programming
	union
	{
		struct
		{
			u8 PROG_GO			:1; //Enables programming for the OTP page selected by OTP_PROG_CTRL[PAGESEL].
			u8 PAGESEL			:1; //Selects which customer OTP page to be programmed.
			u8 RSVD				:6; 
		}Bit;
		u8 Byte;
	}OTP_PROG_CTRL;
	
	union
	{
		struct
		{
			u8 ENABLE			:1; //Executes the OTP ECC test configured by [ENC_DEC] and [DED_SEC] bits
			u8 ENC_DEC			:1; //Sets the encoder/decoder test to run when OTP_ECC_TEST[ENABLE] = 1.
			u8 MANUAL_AUTO		:1;	//Sets the location of the data to use for the ECC test.
			u8 DED_SEC			:1; //Sets the decoder function (SEC or DED) to test
			u8 RSVD				:4; 
		}Bit;
		u8 Byte;
	}OTP_ECC_TEST;
	
	u8 OTP_ECC_DATAIN[9];		//When ECC is enabled in manual mode, CUST_ECC_TEST[MANUAL_AUTO] = 1, OTP_ECC_DATAIN1?
													//registers are used to test the ECC encoder/decoder
	u8 OTP_ECC_DATAOUT[9];		//OTP_ECC_DATAOUT* bytes output the results of the ECC decoder and encoder tests.
	
	union
	{
		struct
		{
			u8 DONE				:1; //Indicates the status of the OTP programming for the selected page
			u8 PROGERR			:1; //Indicates when an error is detected due to incorrect page setting caused by any of the following
			u8 SOVERR			:1;	//A programming voltage stability test is performed before starting the actual OTP programming
			u8 SUVERR			:1; //A programming voltage stability test is performed before starting the actual OTP programming
			u8 OVERR			:1;	//Indicates an overvoltage error detected on the programming voltage during OTP programming
			u8 UVERR			:1; //Indicates an undervoltage error detected on the programming voltage during OTP programming
			u8 OTERR			:1;	//Indicates the die temperature is greater than TOTP_PROG and device does not start OTP programming.
			u8 UNLOCK			:1; //Indicates the OTP programming function unlock status. 
		}Bit;
		u8 Byte;
	}OTP_PROG_STAT;
	
	
	union
	{
		struct
		{
			u8 TRY				:1; //Indicates a first programming attempt for OTP page 1
			u8 OVOK				:1; //Indicates an OTP programming voltage overvoltage condition is detected 
																//during programming attempt for OTP page 1
			u8 UVOK				:1;	//Indicates an OTP programming voltage undervoltage condition is detected 
																//during programming attempt for OTP page 1
			u8 PROGOK			:1; //Indicates the validity for loading for OTP page 1. A valid page indicates that successful programming occurred.
			u8 FMTERR			:1;	//Indicates a formatting error in OTP page 1; that is, when [UVOK] or [OVOK] is set
			u8 LOADERR			:1; //Indicates an error while attempting to load OTP page 1
			u8 LOADWRN			:1;	//Indicates OTP page 1 was loaded but with one or more SEC warnings
			u8 LOADED			:1; //Indicates OTP page 1 has been selected for loading into the related registers.
		}Bit;
		u8 Byte;
	}OTP_CUST1_STAT;
	
	union
	{
		struct
		{
			u8 TRY				:1; //Indicates a first programming attempt for OTP page 1.
			u8 OVOK				:1; //Indicates an OTP programming voltage overvoltage condition is detected 
																//during programming attempt for OTP page 1
			u8 UVOK				:1;	//Indicates an OTP programming voltage undervoltage condition is detected 
																//during programming attempt for OTP page 1
			u8 PROGOK			:1; //Indicates the validity for loading for OTP page 1. A valid page indicates that successful programming occurred.
			u8 FMTERR			:1;	//Indicates a formatting error in OTP page 1; that is, when [UVOK] or [OVOK] is set
			u8 LOADERR			:1; //Indicates an error while attempting to load OTP page 1
			u8 LOADWRN			:1;	//Indicates OTP page 1 was loaded but with one or more SEC warnings
			u8 LOADED			:1; //Indicates OTP page 1 has been selected for loading into the related registers.
		}Bit;
		u8 Byte;
	}OTP_CUST2_STAT;
	
}_Bq79616_RegisterGroup;
extern _Bq79616_RegisterGroup Bq79616_Reg[4];
/**@} */
u8 Bq79616_WakeUp(void);///<BQ79616从shutdown或sleep模式进入wakeup模式，使用wakeup指令
u8 Bq79616_SLP2ACT(void);///<从sleep进入active模式，使用SLP2ACT指令
u8 Bq79616_Main_Config(void);	///<MAIN ADC的寄存器配置
u8 Bq79616_Main_Mears(void);	///<MAIN ADC的采集
u8 Bq79616_AUX_Mears(void);
void Moule_Balance_Time(u16* balance_time,u16* time_set);	///<模组均衡时间设置
u8 Bq79616_ShutDown(void);
u8 Bq79616_Sleep(void);
/********************诊断检验函数************************/
u8 Cell_Vol_Chek(void);	///<对VC和CB检测电压值进行对比，检查是否偏差过大
u8 Cell_LPF_Chek(void);	///<对LPF的检测
u8 Cell_Temp_Chek(void); ///<对GPIO检测温度的值进行对比，检查是否温差过大，注意，此处使用百分比验证
u8 Balance_FET_Chek(void); ///<对CBFET的进行校验
u8 VC_Open_Chek(void);	///<对VC进行开路检验
u8 CB_Open_Chek(void);	///<对CB进行开路检验
void Get_Fault(void);	///<读取故障错误位


